The present invention relates to deriving a fixed delay between multiple clock signals, in particular, to delay locked loop (DLL) circuits.
High speed electronic systems often have critical timing requirements that call for a periodic clock signal having a precise timing relationship with some reference signal. Many high performance integrated circuits present challenges in keeping such integrated circuits synchronized during operation.
The operation of these complex systems require that the components be highly synchronized. In this way, the maximum skew or difference in time between the significant edges of the internal clocking signals of all the components should be minimal. Different components may have different manufacturing parameters. In addition, other factors such as ambient temperature, voltage, and processing variation can lead to large difference in the phases of the internal clocking signals of the different components. Consequently, feeding a system-wide reference clock to the components may not be sufficient to achieve synchronization.
One way synchronization has been achieved is with the use of delay locked loop (DLL) circuits. A DLL typically includes a phase detector that detects the phase difference between an input clock and an output clock signal of the same frequency and generates a digital signal related to the phase difference. The phase difference signal is then in turn used by a delay control block to control a delay chain. A delay chain accordingly advances or delays the timing of the output clock signal with respect to the input clock signal until the rising edge of the output clock signal is coincident with the rising edge of the input clock signal. The phase detector control block and delay chain thus operate in a closed loop to bring the two clock signals into phase and thus synchronize the component whose operations are timed in accordance with the respective clock signals.
In a DLL feedback loop, on-chip delay is often modeled. The modeled delay approximates the actual delay caused by a semiconductor device's circuit components, such as: receiver, a driver, and an off chip driver (OCD), as well as that caused by external termination and load. A delay model often utilizes an inverter chain to account for delay.
Some such DLL feedback loop designs suffer from inaccurate modeling of the actual delay caused by the circuit components. Some such inaccuracies result from variations in technology and unaccounted for temperate effects. Furthermore, some designs are difficult to implement in some systems.
For these and other reasons the need exits for the present invention.